In the field of automotive electronics, a so-called Distributed System Interface (DSI) was developed by Motorola Inc./Freescale Semiconductor Inc. and is a specification for implementing a bus for safety applications. The DSI specification describes bus topology, physical characteristics, message protocols and classes, formats, bit transmission orders and a method of programming devices having programmable addresses.
The DSI is a type of so-called Niche Area Network (NAN) and was designed to interconnect a number of remote sensor devices and actuators with a control module. The DSI provides a highly robust moderate speed interconnection that is also a low cost solution, whilst only using two wires. Furthermore, the DSI is fail safe, deterministic and has good Electromagnetic Compatibility (EMC) characteristics.
A typical application for the DSI is for implementing a bus supporting an airbag system, the airbag system having multiple components that can be embedding in, for example, instrument panels, steering columns and seats.
The DSI implements a master-slave architecture to maintain simplicity of implementation. The DSI also implements Cyclic Redundancy Check (CRC) codes and remote self-diagnostics in order to maintain robustness.
In one typical implementation, a master module is coupled to a first slave module, a second slave module, a third slave module and a fourth slave module in a serial manner. As mentioned above, the bus is implemented on a pair of wires, the pair of wires being used to couple the master module and the first, second, third and fourth slave modules and allow application of a differential voltage signal by the master module. In order to reduce EMC emissions and provide resistance to Electrostatic Discharge (ESD) events, input and output capacitive loads are coupled across pairs of differential input and output terminals of the first, second, third and fourth slave modules. Additionally, a so-called “holding capacitor” is provided in respect of each of the first, second, third and fourth slave modules and is provided to power the slave modules.
The master module comprises an amplifier circuit, for example of the Operational Amplifier (Op-amp) type, and is used to communicate a differential output voltage signal on the bus, via a differential output thereof, to the first, second, third and/or fourth slave modules in accordance with the DSI specification. In this respect, the master module has an idle mode and a signal mode. In the idle mode, the amplifier circuit generates, for example, a 25V differential output voltage, or another value of output voltage depending upon the maximum voltage supply supported by a vehicle in which the bus is provided. However, upon entering the signal mode, the differential output voltage reduces to, for example, 4.5V. Each of the first, second, third and fourth slave modules comprises a comparator circuit that recognises the transition of the differential output voltage signal of the master module and, responsive to the detected transition, enters a respective signal mode.
The bus is a full duplex bus, the master module transmitting to the slave modules using a voltage signal and each of the slave modules using a current signal to transmit to the master module. To this end, the voltage signal used by the master module is a duty cycle modulated signal and the current signal used by the slave modules is an amplitude modulated current signal. In accordance with the DSI specification, responses to commands sent by the master module are sent by the slave modules, during a response time, the response signals being self-synchronised to a falling voltage edge generated by the master module during transmission of a pulse train of any combination of logic ones and zeros.
It is known that the amplifier circuit of the master module is characterised by a number of parameters, including slew rate: the rate of change of voltage with time. When generating a duty cycle modulated signal, the amplifier circuit generates a waveform that comprises a rising edge, a substantially constant level portion, followed by a falling edge, the waveform approximating to a digital pulse. Due to the slew rate of the amplifier circuit, the rising edge is not perfectly vertical, but inclined. Similarly, the falling edge is also sloped due to the slew rate of the amplifier circuit. Furthermore, due to the capacitive loading on the output of the amplifier circuit, the output voltage signal does not reach the voltage level desired in a neat and precise manner and so the output voltage signal possesses a transient or damped oscillation, sometimes referred to as overshoot and undershoot, that exceeds a level desired and then falls back below the level desired before settling at the desired voltage level. The transient therefore has a settling time associated therewith.
During the response time, when the master module is generating the arbitrary pulse train of ones and zeros, the initial, rising, overshoot results in the capacitive load on the master module drawing current to charge the capacitive load, and subsequent, falling, undershoot results in the capacitive load on the master module discharging.
The charging and discharging of the capacitive load results in a current signal being generated on the bus. In the case of the rising overshoot, the current generated corresponds, if detected, to a logic one, whereas in the case of the falling undershoot, the current generated corresponds, if detected, to a logic zero.
Typically, the currents generated as a result of the transient signal are not detected because the transient settles before the falling voltage edge generated by the output of the master module and so are not detected by the master module. However, if the erroneously generated current signals were to be detected by detection circuitry of the master module, the current signal could be misconstrued as a response from one of the slave modules or the current signal could mask or conceal a response from one or more of the slave modules.
As mentioned above, the DSI specification supports moderately high speed communications. However, it is desirable to increase the speed of communications supported by hardware, for example an integrated circuit, implementing the DSI specification. In this respect, it is desirable to support data rates of up to, for example, 200 kbps. When the period of the duty cycle modulated output voltage signal is reduced, the location of the occurrence of the erroneous current signal generated in response to, for example, the undershoot of the output voltage signal of the master module translates to or beyond the location, in time, of the falling voltage edge generated by the master module during the response time. Consequently, the erroneous current signals are detected by the master module and the above-mentioned symptoms associated with detection of the erroneous current signals become problematic.
U.S. Pat. No. 4,169,996 relates to an operational amplifier with slew recovery enhancement. A circuit is disclosed that implements a closed-loop solution comprising a first, inner, feedback loop and a second, outer, feedback loop. However, provision of multiple feedback loops constitutes additional circuit complexity associated with a closed-loop solution. It is, of course, desirable to avoid additional complexity due to die space and cost implications thereof.